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Title:
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Improving The Robustness Of The Register File: a Register File Cache Architecture
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Author:
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Zhuang, Sicong
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Other authors:
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Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors; Canal Corretger, Ramon |
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Abstract:
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This thesis exploits a multi-band cache-like register file architecture to mitigate the potential damage caused by process variations and soft error (single event upsets). An quantitative analysis is conducted to measure the possible gains and loses by incorporating it using simulation results. |
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Subject(s):
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-Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
-Microprocessors
-register file
-process variation
-soft error
-register file
-process variation
-soft error
-Microprocessadors |
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Rights:
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Document type:
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Research/Master Thesis |
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Published by:
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Universitat Politècnica de Catalunya
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