Title:
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Direct instruction wakeup for out-of-order processors
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Author:
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Ramírez, Marco Antonio; Cristal Kestelman, Adrián; Veidenbaum, Alex; Villa, Luis A; Valero Cortés, Mateo
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Other authors:
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Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors; Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
Abstract:
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Instruction queues consume a significant amount of power in high-performance processors, primarily due to instruction wakeup logic access to the queue structures. The wakeup logic delay is also a critical timing parameter. This paper proposes a new queue organization using a small number of successor pointers plus a small number of dynamically allocated full successor bit vectors for cases with a larger number of successors. The details of the new organization are described and it is shown to achieve the performance of CAM-based or full dependency matrix organizations using just one pointer per instruction plus eight full bit vectors. Only two full bit vectors are needed when two successor pointers are stored per instruction. Finally, a design and pre-layout of all critical structures in 70 nm technology was performed for the proposed organization as well as for a CAM-based baseline. The new design is shown to use 1/2 to 1/5th of the baseline instruction queue power, depending on queue size. It is also shown to use significantly less power than the full dependency matrix based design. |
Abstract:
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Peer Reviewed |
Subject(s):
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-Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors -Logic design -Microprocessors -Parallel processing (Electronic computers) -CAM -Direct wakeup -Issue queue -Low-power -Out-of-order processors -Wakeup instructions -Estructura lògica -Microprocessadors -Processament en paral·lel (Ordinadors) |
Rights:
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Document type:
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Article - Published version Conference Object |
Published by:
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Institute of Electrical and Electronics Engineers (IEEE)
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