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dc.contributor | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
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dc.contributor | Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
dc.contributor.author | Seyedi, Azam |
dc.contributor.author | Armejach, Adrià |
dc.contributor.author | Cristal Kestelman, Adrián |
dc.contributor.author | Unsal, Osman Sabri |
dc.contributor.author | Hur, Ibrahim |
dc.contributor.author | Valero Cortés, Mateo |
dc.date | 2011 |
dc.identifier.citation | Seyedi, A., Armejach, A., Cristal, A., Unsal, O., Hur, I., Valero, M. "Circuit design of a dual-versioning L1 data cache for optimistic concurrency". 2011. |
dc.identifier.uri | http://hdl.handle.net/2117/110488 |
dc.language.iso | eng |
dc.relation | UPC-DAC-RR-CAP-2011-9 |
dc.relation | info:eu-repo/grantAgreement/EC/FP7/217068/EU/High Performance and Embedded Architecture and Compilation/HIPEAC |
dc.rights | info:eu-repo/semantics/openAccess |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject | Multiprocessors |
dc.subject | Parallel processing (Electronic computers) |
dc.subject | Data cache design |
dc.subject | Optimistic concurrency |
dc.subject | Parallelism |
dc.subject | Multiprocessadors |
dc.subject | Processament en paral·lel (Ordinadors) |
dc.title | Circuit design of a dual-versioning L1 data cache for optimistic concurrency |
dc.type | info:eu-repo/semantics/publishedVersion |
dc.type | info:eu-repo/semantics/report |
dc.description.abstract |