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dc.contributor | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
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dc.contributor | Universitat Politècnica de Catalunya. DAMA-UPC - Data Management Group |
dc.contributor | Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
dc.contributor.author | Steinhaus, Marc |
dc.contributor.author | Kolla, Reiner |
dc.contributor.author | Larriba Pey, Josep |
dc.contributor.author | Ungerer, Theo |
dc.contributor.author | Valero Cortés, Mateo |
dc.date | 2001 |
dc.identifier.citation | Steinhaus, M., Kolla, R., Larriba, J., Ungerer, T., Valero, M. Transistor count and chip-space estimation of simplescalar-based microprocessor model. A: Workshop on Complexity-Effective Design. "Workshop on Complexity-Effective Design: June 30, 2001 Goteborg, Sweden". Goteborg: 2001, p. 1-15. |
dc.identifier.uri | http://hdl.handle.net/2117/107519 |
dc.language.iso | eng |
dc.rights | info:eu-repo/semantics/openAccess |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject | Microprocessors -- Design and construction |
dc.subject | Transistor count |
dc.subject | Chip-space estimation |
dc.subject | Simplescalar-based microprocessor model |
dc.subject | Microprocessadors -- Disseny i construcció |
dc.title | Transistor count and chip-space estimation of simplescalar-based microprocessor model |
dc.type | info:eu-repo/semantics/submittedVersion |
dc.type | info:eu-repo/semantics/conferenceObject |
dc.description.abstract |