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dc.contributor | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
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dc.contributor | Universitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors |
dc.contributor.author | Sánchez Navarro, F. Jesús |
dc.contributor.author | González Colás, Antonio María |
dc.date | 2000 |
dc.identifier.citation | Sánchez, F., González, A. The effectiveness of loop unrolling for modulo scheduling in clustered VLIW architectures. A: International Conference on Parallel Processing. "2000 International Conference on Parallel Processing: 21-24 August 2000, Toronto, Canada: proceedings". Toronto: Institute of Electrical and Electronics Engineers (IEEE), 2000, p. 555-562. |
dc.identifier.citation | 0-7695-0768-9 |
dc.identifier.citation | 10.1109/ICPP.2000.876173 |
dc.identifier.uri | http://hdl.handle.net/2117/105275 |
dc.language.iso | eng |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) |
dc.relation | http://ieeexplore.ieee.org/document/876173/ |
dc.rights | info:eu-repo/semantics/openAccess |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject | Parallel processing (Electronic computers) |
dc.subject | VLIW |
dc.subject | Registers |
dc.subject | Processor scheduling |
dc.subject | Delay effects |
dc.subject | Communication channels |
dc.subject | Proposals |
dc.subject | Pipeline processing |
dc.subject | Electronic mail |
dc.subject | Continuous improvement |
dc.subject | Processament en paral·lel (Ordinadors) |
dc.title | The effectiveness of loop unrolling for modulo scheduling in clustered VLIW architectures |
dc.type | info:eu-repo/semantics/publishedVersion |
dc.type | info:eu-repo/semantics/conferenceObject |
dc.description.abstract | |
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