To access the full text documents, please follow this link: http://hdl.handle.net/2117/104033
dc.contributor | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
---|---|
dc.contributor | Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
dc.contributor.author | Zalamea León, Francisco Javier |
dc.contributor.author | Llosa Espuny, José Francisco |
dc.contributor.author | Ayguadé Parra, Eduard |
dc.contributor.author | Valero Cortés, Mateo |
dc.date | 2001 |
dc.identifier.citation | Zalamea, F., Llosa, J., Ayguadé, E., Valero, M. Modulo scheduling with integrated register spilling for clustered VLIW architectures. A: Annual IEEE/ACM International Symposium on Microarchitecture. "34th ACM/IEEE International Symposium on Microarchitecture, 2001, MICRO-34: proceedings". Austin: Institute of Electrical and Electronics Engineers (IEEE), 2001, p. 160-169. |
dc.identifier.citation | 0-7965-1369-7 |
dc.identifier.citation | 10.1109/MICRO.2001.991115 |
dc.identifier.uri | http://hdl.handle.net/2117/104033 |
dc.language.iso | eng |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) |
dc.relation | http://ieeexplore.ieee.org/xpl/abstractKeywords.jsp?arnumber=991115 |
dc.rights | info:eu-repo/semantics/openAccess |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject | Parallel processing (Electronic computers) |
dc.subject | Microprocessors -- Energy consumption |
dc.subject | Parallel architectures |
dc.subject | Power consumption |
dc.subject | Processor scheduling |
dc.subject | Storage management |
dc.subject | Processament en paral·lel (Ordinadors) |
dc.subject | Microprocessadors -- Consum d'energia |
dc.title | Modulo scheduling with integrated register spilling for clustered VLIW architectures |
dc.type | info:eu-repo/semantics/publishedVersion |
dc.type | info:eu-repo/semantics/conferenceObject |
dc.description.abstract | |
dc.description.abstract |