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dc.contributor | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
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dc.contributor | Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
dc.contributor.author | Valero Cortés, Mateo |
dc.contributor.author | Peiron Guàrdia, Montse |
dc.contributor.author | Ayguadé Parra, Eduard |
dc.date | 1994 |
dc.identifier.citation | Valero, M., Peiron, M., Ayguadé, E. Access to vectors in multi-module memories. A: Euromicro International Conference on Parallel, Distributed, and Network-Based Processing. "Second Euromicro Workshop on Parallel and Distributed Processing: proceedings". Málaga: Institute of Electrical and Electronics Engineers (IEEE), 1994, p. 228-236. |
dc.identifier.citation | 0-8186-5370-1 |
dc.identifier.citation | 10.1109/EMPDP.1994.592494 |
dc.identifier.uri | http://hdl.handle.net/2117/103561 |
dc.language.iso | eng |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) |
dc.relation | http://ieeexplore.ieee.org/document/592494/ |
dc.rights | info:eu-repo/semantics/openAccess |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject | Cache memory |
dc.subject | Multiprocessors |
dc.subject | Bandwidth |
dc.subject | Memory management |
dc.subject | Multiprocessing systems |
dc.subject | Delay |
dc.subject | Intelligent networks |
dc.subject | Multiprocessor interconnection networks |
dc.subject | Degradation |
dc.subject | Computer networks |
dc.subject | Interleaved codes |
dc.subject | Memòria ràpida de treball (Informàtica) |
dc.subject | Multiprocessadors |
dc.title | Access to vectors in multi-module memories |
dc.type | info:eu-repo/semantics/publishedVersion |
dc.type | info:eu-repo/semantics/conferenceObject |
dc.description.abstract | |
dc.description.abstract |