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Title:
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Exploiting pseudo-schedules to guide data dependence graph partitioning
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Author:
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Aleta Ortega, Alexandre; Codina Viñas, Josep M.; Sánchez Navarro, F. Jesús; González Colás, Antonio María; David, Kaeli
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Other authors:
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Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors; Universitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors |
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Abstract:
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This paper presents a new modulo scheduling algorithm for clustered microarchitectures. The main feature of the proposed scheme is that the assignment of instructions to clusters is done by means of graph partitioning algorithms that are guided by a pseudo-scheduler. This pseudo-scheduler is a simplified version of the full instruction scheduler and estimates key constraints that would be encountered in the final schedule. The final scheduling process is bi-directional and includes on-the-fly spill code generation. The proposed scheme is evaluated against previous scheduling approaches using the SPECfp95 benchmark suite. Our modeling results show that better schedules are obtained for most programs across a range of different architectures. For a 4-cluster VLIW architecture with 32 registers and a 2-cycle inter-cluster communication delay we obtain an average speedup of 38.5%. |
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Abstract:
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Peer Reviewed |
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Subject(s):
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-Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
-Embedded computer systems
-Microprocessors
-Processor scheduling
-Microarchitecture
-VLIW
-Registers
-Computer architecture
-Delay
-Scheduling algorithm
-Floating-point arithmetic
-Clustering algorithms
-Partitioning algorithms
-Ordinadors immersos, Sistemes d'
-Microprocessadors |
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Rights:
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Document type:
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Article - Published version
Conference Object |
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Published by:
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Institute of Electrical and Electronics Engineers (IEEE)
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