Title:
|
Synthesis of timing paths with delays adaptable to integrated circuit variability
|
Author:
|
Moreno Vega, Alberto
|
Other authors:
|
Universitat Politècnica de Catalunya. Departament de Ciències de la Computació; Cortadella, Jordi |
Abstract:
|
This project proposes to substitute the Clock of a circuit for a Ring Oscillator. This Ring Oscillator is designed to be susceptible to variability in the same way than the rest of the system, allowing to drastically reduce variability guard band margins at design stage. |
Subject(s):
|
-Àrees temàtiques de la UPC::Informàtica -Integrated circuits -variabilitat -camí crític -process corner -beam search -ring oscillator -rellotges adaptatius -llibreria de standard cells -Variability -critical path -process corner -adaptive clocks -standard cell library -Circuits integrats |
Rights:
|
|
Document type:
|
Research/Master Thesis |
Published by:
|
Universitat Politècnica de Catalunya
|
Share:
|
|