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dc.contributor | Universitat Politècnica de Catalunya. Departament de Ciències de la Computació |
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dc.contributor | Universitat Politècnica de Catalunya. ALBCOM - Algorismia, Bioinformàtica, Complexitat i Mètodes Formals |
dc.contributor.author | Cortadella, Jordi |
dc.date | 2013-11 |
dc.identifier.citation | Cortadella, J. Area-optimal transistor folding for 1-D gridded cell design. "IEEE transactions on computer-aided design of integrated circuits and systems", Novembre 2013, vol. 32, núm. 11, p. 1708-1721. |
dc.identifier.citation | 0278-0070 |
dc.identifier.citation | 10.1109/TCAD.2013.2269680 |
dc.identifier.uri | http://hdl.handle.net/2117/27265 |
dc.language.iso | eng |
dc.relation | https://ieeexplore.ieee.org/document/6634571 |
dc.rights | info:eu-repo/semantics/openAccess |
dc.subject | Àrees temàtiques de la UPC::Enginyeria electrònica::Components electrònics::Transistors |
dc.subject | Transistors |
dc.subject | Cell generation |
dc.subject | Design for manufacturability |
dc.subject | Linear programming |
dc.subject | Transistor folding |
dc.subject | Transistor sizing |
dc.subject | Transistors |
dc.title | Area-optimal transistor folding for 1-D gridded cell design |
dc.type | info:eu-repo/semantics/submittedVersion |
dc.type | info:eu-repo/semantics/article |
dc.description.abstract | |
dc.description.abstract |