Lithography parametric yield estimation model to predict layout pattern distortions with a reduced set of lithography simulations

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dc.contributor	Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica
dc.contributor	Universitat Politècnica de Catalunya. HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions
dc.contributor.author	Gómez Fernández, Sergio
dc.contributor.author	Moll Echeto, Francisco de Borja
dc.contributor.author	Mauricio Ferré, Juan
dc.date	2014-07-01
dc.identifier.citation	Gomez, S.; Moll, F.; Mauricio, J. Lithography parametric yield estimation model to predict layout pattern distortions with a reduced set of lithography simulations. "Journal of micro/nanolithography, MEMS and MOEMS", 01 Juliol 2014, vol. 13, núm. 3.
dc.identifier.citation	1932-5150
dc.identifier.citation	10.1117/1.JMM.13.3.033016
dc.identifier.uri	http://hdl.handle.net/2117/26792
dc.language.iso	eng
dc.relation	http://nanolithography.spiedigitallibrary.org/article.aspx?articleid=1906672
dc.rights	info:eu-repo/semantics/openAccess
dc.subject	Àrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats
dc.subject	Nanoelectronics
dc.subject	Lithography
dc.subject	Design for manufacturability
dc.subject	Lithography hotspots
dc.subject	Yield estimation
dc.subject	Layout design
dc.subject	Nanoelectrònica
dc.subject	Litografia
dc.title	Lithography parametric yield estimation model to predict layout pattern distortions with a reduced set of lithography simulations
dc.type	info:eu-repo/semantics/submittedVersion
dc.type	info:eu-repo/semantics/article
dc.description.abstract	A lithography parametric yield estimation model is presented to evaluate the lithography distortion in a printed layout due to lithography hotspots. The aim of the proposed yield model is to provide a new metric that enables the possibility to objectively compare the lithography quality of different layout design implementations. Moreover, we propose a pattern construct classifier to reduce the set of lithography simulations necessary to estimate the litho degradation. The application of the yield model is demonstrated for different layout configurations showing that a certain degree of layout regularity improves the parametric yield and increases the number of good dies per wafer. (C) 2014 Society of Photo-Optical Instrumentation Engineers (SPIE)
dc.description.abstract	Peer Reviewed

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