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dc.contributor | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
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dc.contributor | Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
dc.contributor.author | Ratkovic, Ivan |
dc.contributor.author | Palomar Pérez, Óscar |
dc.contributor.author | Stanic, Milan |
dc.contributor.author | Unsal, Osman Sabri |
dc.contributor.author | Cristal Kestelman, Adrián |
dc.contributor.author | Valero Cortés, Mateo |
dc.date | 2013 |
dc.identifier.citation | Ratkovic, I. [et al.]. On the selection of adder unit in energy efficient vector processing. A: International Symposium on Quality Electronic Design. "Proceedings of the Fourteenth International Symposium on Quality Electronic Design: ISQED 2013: March 4-6, 2013: Santa Clara, California, USA". Santa Clara, California: Institute of Electrical and Electronics Engineers (IEEE), 2013, p. 143-150. |
dc.identifier.citation | 978-1-4673-4951-2 |
dc.identifier.citation | 10.1109/ISQED.2013.6523602 |
dc.identifier.uri | http://hdl.handle.net/2117/24650 |
dc.language.iso | eng |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) |
dc.relation | http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6523602 |
dc.relation | info:eu-repo/grantAgreement/EC/FP7/287759/EU/High Performance and Embedded Architecture and Compilation/HIPEAC |
dc.rights | Attribution-NonCommercial-NoDerivs 3.0 Spain |
dc.rights | info:eu-repo/semantics/openAccess |
dc.rights | http://creativecommons.org/licenses/by-nc-nd/3.0/es/ |
dc.subject | Àrees temàtiques de la UPC::Informàtica |
dc.subject | Microprocessors |
dc.subject | Logic design |
dc.subject | Adders |
dc.subject | Logic design |
dc.subject | Microprocessor chips |
dc.subject | Microprocessadors |
dc.subject | Estructura lògica |
dc.title | On the selection of adder unit in energy efficient vector processing |
dc.type | info:eu-repo/semantics/publishedVersion |
dc.type | info:eu-repo/semantics/conferenceObject |
dc.description.abstract | |
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