This paper presents a new proposal for hiding the cryptographic key, when the so-called side-channel attacks (SCAs) are applied to break the security of AES-128. The algorithm was executed on MicroBlaze, but the proposed method is generic and can be extended to any other microprocessor. SCAs are based on examining the correlation produced between the data and operations performed by the microprocessor and its actual power consumption. Traditionally, such weakness is counteracted by introducing countermeasures addressed to reduce as much as possible this correlation, making data and power consumption independent. On the contrary, the proposal presented in this paper introduces some modifications in the AES algorithm. These changes aim at concealing the true key by reinforcing the correlation coefficient in such a way that a classical attack leads to a false key. This way, the system misleads the attacker and apparently behaves as an unprotected system that, in fact, reveals a false positive. The complete system was built on a Virtex-5 FPGA. Experimental results show the strength of our implementation, which is capable of successfully hiding the true cryptographic key.