Title:
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Analysis of the Task Superscalar architecture hardware design
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Author:
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Yazdanpanah Ahmadabadi, Fahimeh; Jiménez González, Daniel; Álvarez Martínez, Carlos; Etsion, Yoav; Badia Sala, Rosa Maria
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Other authors:
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Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors; Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
Abstract:
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In this paper, we analyze the operational flow of two hardware implementations of the Task Superscalar architecture. The Task Superscalar is an experimental task based dataflow scheduler that dynamically detects inter-task data dependencies, identifies task-level parallelism, and executes tasks in the out-of-order manner. In this paper, we present a base implementation of the Task Superscalar architecture, as well as a new design with improved performance. We study the behavior of processing some dependent and non-dependent tasks with both base and improved hardware designs and present the simulation results compared with the results of the runtime implementation. |
Abstract:
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This work is supported by the Ministry of Science and Technology of Spain and the European Union (FEDER funds) under contract TIN2007-60625, by the Generalitat de Catalunya (contract 2009-SGR-980), and by the European FP7 project TERAFLUX id. 249013, http://www.tera ux.eu. We would also like to thank the Xilinx University Program for its hardware and software donations. |
Subject(s):
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-Àrees temàtiques de la UPC::Informàtica::Hardware -VHDL (Computer hardware description language) -Task Superscalar -Hardware task scheduler -VHDL -VHDL (Llenguatge de descripció de maquinari) |
Rights:
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Document type:
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Article - Submitted version Conference Object |
Published by:
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Springer
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