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dc.contributor | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
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dc.contributor | Universitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors |
dc.contributor.author | Jaksic, Zoran |
dc.contributor.author | Canal Corretger, Ramon |
dc.date | 2014 |
dc.identifier.citation | Jaksic, Z.; Canal, R. DRAM-based coherent caches and how to take advantage of the coherence protocol to reduce the refresh energy. A: Design, Automation and Test in Europe. "Design, Automation and Test in Europe: proceedings: Dresden, Germany: March 24-28, 2014". Dreden: European Interactive Digital Advertising Alliance (EDAA), 2014. |
dc.identifier.citation | 978-398153702-4 |
dc.identifier.citation | 10.7873/DATE2014.094 |
dc.identifier.uri | http://hdl.handle.net/2117/23202 |
dc.language.iso | eng |
dc.publisher | European Interactive Digital Advertising Alliance (EDAA) |
dc.relation | http://dl.acm.org/citation.cfm?id=2616706 |
dc.rights | Attribution-NonCommercial-NoDerivs 3.0 Spain |
dc.rights | info:eu-repo/semantics/openAccess |
dc.rights | http://creativecommons.org/licenses/by-nc-nd/3.0/es/ |
dc.subject | Àrees temàtiques de la UPC::Enginyeria de la telecomunicació::Telemàtica i xarxes d'ordinadors::Protocols de comunicació |
dc.subject | Àrees temàtiques de la UPC::Informàtica |
dc.subject | Memory management (Computer science) |
dc.subject | Energy conservation |
dc.subject | 3T DRAM |
dc.subject | 6T SRAM |
dc.subject | cache coherence |
dc.subject | FinFETs |
dc.subject | retention time |
dc.subject | Gestió de memòria (Informàtica) |
dc.subject | Energia -- Estalvi |
dc.title | DRAM-based coherent caches and how to take advantage of the coherence protocol to reduce the refresh energy |
dc.type | info:eu-repo/semantics/publishedVersion |
dc.type | info:eu-repo/semantics/conferenceObject |
dc.description.abstract | |
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