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dc.contributor | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
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dc.contributor.author | Seyedi, Azam |
dc.contributor.author | Yalcin, Gulay |
dc.contributor.author | Unsal, Osman Sabri |
dc.contributor.author | Cristal Kestelman, Adrián |
dc.date | 2013 |
dc.identifier.citation | Seyedi, A. [et al.]. Circuit design of a novel adaptable and reliable L1 data cache. A: ACM Great Lakes Symposium on VLSI. "Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI". Parias: 2013, p. 333-334. |
dc.identifier.citation | 10.1145/2483028.2483129 |
dc.identifier.uri | http://hdl.handle.net/2117/23133 |
dc.language.iso | eng |
dc.relation | info:eu-repo/grantAgreement/EC/FP7/287759/EU/High Performance and Embedded Architecture and Compilation/HIPEAC |
dc.rights | info:eu-repo/semantics/openAccess |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Sistemes d'informació::Emmagatzematge i recuperació de la informació |
dc.subject | Cache memory |
dc.subject | CMOS integrated circuits |
dc.subject | Design |
dc.subject | Electric power supplies to apparatus |
dc.subject | Fault tolerance |
dc.subject | Fault tolerant computer systems |
dc.subject | Separation |
dc.subject | Memòria ràpida de treball (Informàtica) |
dc.title | Circuit design of a novel adaptable and reliable L1 data cache |
dc.type | info:eu-repo/semantics/publishedVersion |
dc.type | info:eu-repo/semantics/conferenceObject |
dc.description.abstract |