Design-oriented analysis of quantization-induced limit cycles in a multiple-sampled digitally controlled buck converter

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To access the full text documents, please follow this link: http://hdl.handle.net/2117/22888

dc.contributor	Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica
dc.contributor	Universitat Politècnica de Catalunya. EPIC - Energy Processing and Integrated Circuits
dc.contributor.author	Bradley, Mark
dc.contributor.author	Alarcón Cot, Eduardo José
dc.contributor.author	Feely, Orla
dc.date	2014-04-01
dc.identifier.citation	Bradley, M.; Alarcon, E.; Feely, O. Design-oriented analysis of quantization-induced limit cycles in a multiple-sampled digitally controlled buck converter. "IEEE transactions on circuits and systems I: regular papers", 01 Abril 2014, vol. 61, núm. 4, p. 1192-1205.
dc.identifier.citation	1549-8328
dc.identifier.citation	10.1109/TCSI.2013.2283671
dc.identifier.uri	http://hdl.handle.net/2117/22888
dc.language.iso	eng
dc.relation	http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6642152
dc.rights	Attribution-NonCommercial-NoDerivs 3.0 Spain
dc.rights	info:eu-repo/semantics/openAccess
dc.rights	http://creativecommons.org/licenses/by-nc-nd/3.0/es/
dc.subject	Àrees temàtiques de la UPC::Enginyeria electrònica::Electrònica de potència
dc.subject	Digital control system
dc.subject	Voltage-controlled oscillators
dc.subject	DC-DC power converters
dc.subject	Digital control
dc.subject	Limit cycles
dc.subject	Nonlinear dynamics
dc.subject	Quantization
dc.subject	Control digital
dc.subject	Oscil·ladors de voltatge controlat
dc.title	Design-oriented analysis of quantization-induced limit cycles in a multiple-sampled digitally controlled buck converter
dc.type	info:eu-repo/semantics/publishedVersion
dc.type	info:eu-repo/semantics/article
dc.description.abstract	Digital control of switching power converters is an area which has seen increased attention in recent years. However, quantization in the feedback loop from the analog-to-digital (A/D) converter and the digital pulse width modulator (DPWM) may cause limit cycle oscillations to manifest, which are generally seen as being undesirable. This paper presents an analysis of the limit cycle behavior found in a multiple-sampled digitally controlled buck converter. The limit cycles which may arise in the system are characterized and conditions to prevent these oscillations from occurring are presented. © 2004-2012 IEEE.
dc.description.abstract	Peer Reviewed

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