Impact of finfet and III-V/Ge technology on logic and memory cell behavior

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To access the full text documents, please follow this link: http://hdl.handle.net/2117/21907

dc.contributor	Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica
dc.contributor	Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.contributor	Universitat Politècnica de Catalunya. HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions
dc.contributor	Universitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors
dc.contributor.author	Amat Bertran, Esteve
dc.contributor.author	Calomarde Palomino, Antonio
dc.contributor.author	García Almudéver, Carmen
dc.contributor.author	Aymerich Capdevila, Nivard
dc.contributor.author	Canal Corretger, Ramon
dc.contributor.author	Rubio Sola, Jose Antonio
dc.date	2013-11-20
dc.identifier.citation	Amat, E. [et al.]. Impact of finfet and III-V/Ge technology on logic and memory cell behavior. "IEEE transactions on device and materials reliability", 20 Novembre 2013, vol. 14, núm. 1, p. 1-15.
dc.identifier.citation	1530-4388
dc.identifier.citation	10.1109/TDMR.2013.2291410
dc.identifier.uri	http://hdl.handle.net/2117/21907
dc.language.iso	eng
dc.relation	http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6670777
dc.relation	info:eu-repo/grantAgreement/EC/FP7/248789/EU/TERASCALE RELIABLE ADAPTIVE MEMORY SYSTEMS/TRAMS
dc.rights	Attribution-NonCommercial-NoDerivs 3.0 Spain
dc.rights	info:eu-repo/semantics/openAccess
dc.rights	http://creativecommons.org/licenses/by-nc-nd/3.0/es/
dc.subject	Àrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats
dc.subject	Integrated circuits
dc.subject	DRAM
dc.subject	III–V semiconductor materials
dc.subject	Integrated circuit reliability
dc.subject	Ring oscillators
dc.subject	Circuits integrats
dc.title	Impact of finfet and III-V/Ge technology on logic and memory cell behavior
dc.type	info:eu-repo/semantics/publishedVersion
dc.type	info:eu-repo/semantics/article
dc.description.abstract	In this work, we assess the performance of a ring oscillator and a DRAM cell when they are implemented with different technologies (planar CMOS, FinFET and III-V MOSFETs), and subjected to different reliability scenarios (variability and soft errors). FinFET-based circuits show the highest robustness against variability and soft error environments.
dc.description.abstract	Peer Reviewed

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