Future computing systems based on new emerging nanotechnologies will have to rely on very high failure rate devices. Therefore, the study of fault-tolerant architectures is of great interest today. One of the most challenging problems of this research area consists in finding the fundamental error bounds beyond which reliable computation is not possible. In the literature we can find the exact error threshold for circuits built out of noisy NAND gates under the von Neumann's probabilistic computing framework. In this paper we extend this result for asymmetric error designs and demonstrate that it is possible to compute reliably with 2-input noisy NAND gates beyond the well known error bound: ∈* = (3 - √7)/4.

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