This paper presents a novel technique for the fabrication of ultrahigh capacitance structures based on macroporous silicon. Electrochemical etching is used to create a 3-D template in silicon. These structures reach high specific capacitances and can be incorporated into integrated circuits. Very low series resistance is attained using a metal electrode. The fabrication technology uses standard UV lithography for silicon patterning, and a low-temperature electroplating process for the electrode formation. Devices have been fabricated with several insulator thicknesses to demonstrate the technology. The fabricated devices have a pore diameter of 3 μm arranged in a square lattice of 4-μm pitch, achieving capacitance density up to 110 nF/mm2. Further gains in capacitance can be obtained by reducing pore size and increasing pore density, and also using alternate geometries for the macroporous silicon template. Moreover, to increase capacitance, the use of alternative dielectrics, like high- k materials, is discussed.

Peer Reviewed