Yield estimation model for lithography hotspot distortions

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Title:	Yield estimation model for lithography hotspot distortions
Author:	Gómez Fernández, Sergio; Moll Echeto, Francisco de Borja
Other authors:	Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica; Universitat Politècnica de Catalunya. HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions
Abstract:	A yield formulation model to estimate the amount of lithography distortion expected in a printed layout is proposed. The yield formulation relates the probability of non-failure of a lithography hotspot with the yield loss. The application of the yield model is demonstrated for three different layout configurations showing that unidimensional designs may improve manufacturing yield.
Subject(s):	-Àrees temàtiques de la UPC::Enginyeria electrònica -Àrees temàtiques de la UPC::Enginyeria dels materials -Hot spot -Manufacturing yield -Yield estimation -Yield loss -Yield modeling -Litografia per feix d'electrons -Litografia
Rights:	Attribution-NonCommercial-NoDerivs 3.0 Spain http://creativecommons.org/licenses/by-nc-nd/3.0/es/
Document type:	Article - Published version Article
Published by:	Institution of Electrical Engineers
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