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dc.contributor | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
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dc.contributor | Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
dc.contributor.author | Caballero, Diego |
dc.contributor.author | Duran González, Alejandro |
dc.contributor.author | Martorell Bofill, Xavier |
dc.date | 2013 |
dc.identifier.citation | Caballero, D.; Duran, A.; Martorell, X. An OpenMP* barrier using SIMD instructions for Intel® Xeon Phi™ coprocessor. A: International Workshop on OpenMP. "OpenMP in the era of low power devices and accelerators: 9th International Workshop on OpenMP, IWOMP 2013: Canberra, ACT, Australia: September 2013: Proceedings". Canberra: Springer, 2013, p. 99-113. |
dc.identifier.citation | 978-3-642-40697-3 |
dc.identifier.citation | 10.1007/978-3-642-40698-0_8 |
dc.identifier.uri | http://hdl.handle.net/2117/20295 |
dc.language.iso | eng |
dc.publisher | Springer |
dc.relation | http://link.springer.com/chapter/10.1007%2F978-3-642-40698-0_8 |
dc.relation | info:eu-repo/grantAgreement/EC/FP7/287759/EU/High Performance and Embedded Architecture and Compilation/HIPEAC |
dc.rights | Attribution-NonCommercial-NoDerivs 3.0 Spain |
dc.rights | info:eu-repo/semantics/openAccess |
dc.rights | http://creativecommons.org/licenses/by-nc-nd/3.0/es/ |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors::Arquitectures paral·leles |
dc.subject | Supercomputers |
dc.subject | Barrier |
dc.subject | combining tree |
dc.subject | Intel® Many Integrated Core Architecture |
dc.subject | Intel® Xeon Phi™ coprocessor |
dc.subject | many-cores |
dc.subject | OpenMP* |
dc.subject | SIMD |
dc.subject | synchronisation primitives |
dc.subject | Supercomputadors |
dc.title | An OpenMP* barrier using SIMD instructions for Intel® Xeon Phi™ coprocessor |
dc.type | info:eu-repo/semantics/publishedVersion |
dc.type | info:eu-repo/semantics/conferenceObject |
dc.description.abstract | |
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