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dc.contributor | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
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dc.contributor | Universitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors |
dc.contributor.author | Jing, Naifeng |
dc.contributor.author | Shen, Yao |
dc.contributor.author | Lu, Yao |
dc.contributor.author | Ganapathy, Shrikanth |
dc.contributor.author | Mao, Zhigang |
dc.contributor.author | Guo, Minyi |
dc.contributor.author | Canal Corretger, Ramon |
dc.contributor.author | Liang, Xiaoyao |
dc.date | 2013 |
dc.identifier.citation | Jing, N. [et al.]. An energy-efficient and scalable eDRAM-based register file architecture for GPGPU. A: Annual International Symposium on Computer Architecture. "ISCA 2013: the 40th Annual International Symposium on Computer Architecture: conference proceedings: June 23-27, 2013: Tel-Aviv, Israel". Tel-Aviv: ACM, 2013, p. 344-355. |
dc.identifier.citation | 978-1-4503-2079-5 |
dc.identifier.citation | 10.1145/2485922.2485952 |
dc.identifier.uri | http://hdl.handle.net/2117/20247 |
dc.language.iso | eng |
dc.publisher | ACM |
dc.relation | http://dl.acm.org/citation.cfm?doid=2485922.2485952 |
dc.rights | Attribution-NonCommercial-NoDerivs 3.0 Spain |
dc.rights | info:eu-repo/semantics/openAccess |
dc.rights | http://creativecommons.org/licenses/by-nc-nd/3.0/es/ |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject | Computer architecture |
dc.subject | Program processors |
dc.subject | Computer architecture |
dc.subject | Data processing |
dc.subject | Energy efficiency |
dc.subject | Logic design |
dc.subject | Arquitectura d'ordinadors |
dc.title | An energy-efficient and scalable eDRAM-based register file architecture for GPGPU |
dc.type | info:eu-repo/semantics/publishedVersion |
dc.type | info:eu-repo/semantics/conferenceObject |
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