Technical Report

Digital CMOS Integrated Circuits (ICs) suffer from serious layout features printability issues associated to the lithography manufacturing process. Regular layout designs are emerging as alternative solutions to reduce these ICs systematic subwavelength lithography failures. However, there is no metric to evaluate and compare the layout regularity of those regular designs. In this paper we propose a new layout regularity metric called Fixed Origin Corner Square Inspection (FOCSI). FOCSI allows the comparison and quantification of designs in terms of regularity and for any given degree of granularity. When FOCSI is oriented to the evaluation of regularity while applying Lithography Enhancement Techniques, it comprehends layout layers measurements considering the optical interaction length and combines them to obtain the complete layout regularity measure. Examples are provided for 32-bit adders in the 90 nm technology node for the Standard Cell approach and for Via-Configurable Transistor Array regular designs. We show how layouts can be sorted accurately even if their degree of regularity is similar.