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dc.contributor | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
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dc.contributor | Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
dc.contributor.author | Vallejo, Enrique |
dc.contributor.author | Sanyal, Sutirtha |
dc.contributor.author | Harris, Tim |
dc.contributor.author | Vallejo, Fernando |
dc.contributor.author | Beivide, Ramón |
dc.contributor.author | Unsal, Osman Sabri |
dc.contributor.author | Cristal Kestelman, Adrián |
dc.contributor.author | Valero Cortés, Mateo |
dc.date | 2011-06 |
dc.identifier.citation | Vallejo, E. [et al.]. Hybrid transactional memory with pessimistic concurrency control. "International journal of parallel programming", Juny 2011, vol. 39, núm. 3, p. 375-396. |
dc.identifier.citation | 0885-7458 |
dc.identifier.citation | 10.1007/s10766-010-0158-x |
dc.identifier.uri | http://hdl.handle.net/2117/13110 |
dc.language.iso | eng |
dc.relation | https://posgrado.escom.ipn.mx/biblioteca/Hybrid%20Transactional%20Memory%20with%20Pessimistic.pdf |
dc.relation | info:eu-repo/grantAgreement/EC/FP7/217068/EU/High Performance and Embedded Architecture and Compilation/HIPEAC |
dc.rights | info:eu-repo/semantics/openAccess |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject | Computer storage devices -- Design and construction |
dc.subject | Hybrid transactional memory |
dc.subject | Pessimistic concurrency control |
dc.subject | Writer starvation |
dc.subject | Directory reservation |
dc.subject | Memòria transaccional |
dc.title | Hybrid transactional memory with pessimistic concurrency control |
dc.type | info:eu-repo/semantics/publishedVersion |
dc.type | info:eu-repo/semantics/article |
dc.description.abstract | |
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