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dc.contributor | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
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dc.contributor | Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
dc.contributor.author | Cakarevic, Vladimir |
dc.contributor.author | Radojkovic, Petar |
dc.contributor.author | Verdú Mulà, Javier |
dc.contributor.author | Pajuelo González, Manuel Alejandro |
dc.contributor.author | Gioiosa, Roberto |
dc.contributor.author | Cazorla Almeida, Francisco Javier |
dc.contributor.author | Nemirovsky, Mario |
dc.contributor.author | Valero Cortés, Mateo |
dc.date | 2008 |
dc.identifier.citation | Cakarevic, V. [et al.]. Understanding the overhead of the spin-lock loop in CMT architectures. A: Workshop on the Interaction between Operating Systems and Computer Architecture. "8th Workshop on the Interaction between Operating Systems and Computer Architecture". Beijing: 2008, p. 1-0. |
dc.identifier.uri | http://hdl.handle.net/2117/8373 |
dc.language.iso | eng |
dc.relation | http://www.ideal.ece.ufl.edu/workshops/wiosca08/ |
dc.rights | info:eu-repo/semantics/openAccess |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject | CMT architectures |
dc.subject | Arquitectura d'ordinadors -- Avaluació |
dc.title | Understanding the overhead of the spin-lock loop in CMT architectures |
dc.type | info:eu-repo/semantics/publishedVersion |
dc.type | info:eu-repo/semantics/conferenceObject |
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