Diagnosis of full open defects in interconnecting lines

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To access the full text documents, please follow this link: http://hdl.handle.net/2117/7733

dc.contributor	Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica
dc.contributor	Universitat Politècnica de Catalunya. Departament de Disseny i Programació de Sistemes Electrònics
dc.contributor	Universitat Politècnica de Catalunya. QINE - Disseny de Baix Consum, Test, Verificació i Circuits Integrats de Seguretat
dc.contributor.author	Rodríguez Montañés, Rosa
dc.contributor.author	Arumi Delgado, Daniel
dc.contributor.author	Figueras Pàmies, Joan
dc.contributor.author	Eichenberger, Stefan
dc.contributor.author	Hora, Camelia
dc.contributor.author	Kruseman, Bram
dc.contributor.author	Lousberg, M.
dc.contributor.author	Majhi, A.K.
dc.date	2007-05-31
dc.identifier.citation	Rodríguez, R. [et al.]. Diagnosis of full open defects in interconnecting lines. A: IEEE VLSI Test Symposium. "25th IEEE VLSI Test Symposium". Berkeley: IEEE, 2007, p. 1-6.
dc.identifier.citation	0-7695-2812-0
dc.identifier.uri	http://hdl.handle.net/2117/7733
dc.language.iso	eng
dc.publisher	IEEE
dc.rights	info:eu-repo/semantics/openAccess
dc.subject	Àrees temàtiques de la UPC::Enginyeria electrònica::Circuits electrònics
dc.subject	Metal oxide semiconductors, Complementary
dc.subject	Integrated circuits
dc.subject	Metall-òxid-semiconductors complementaris
dc.subject	Circuits integrats
dc.title	Diagnosis of full open defects in interconnecting lines
dc.type	info:eu-repo/semantics/publishedVersion
dc.type	info:eu-repo/semantics/conferenceObject
dc.description.abstract	Best Paper Award al millor article del congrés IEEE VLSI Test Symposium 2007
dc.description.abstract	A proposal for enhancing the diagnosis of full open defects in interconnecting lines of CMOS circuits is presented. The defective line is first classified as fully opened by means of a logic-based diagnosis tool (Faloc). The proposal is based on the division of the defective line into a number of segments. The selected group of segments is derived from the topology of the line and its surrounding circuitry. The logical information related to the neighbouring metal lines for each considered test pattern is taken into account. With the proposed diagnosis methodology, a set of likely locations for the open defect on the line is obtained. A ranking between the set of possible locations is presented based on the analysis of the quiescent current consumption of the circuit under test. Examples are presented in which the use of the diagnosis methodology is shown to discriminate between different locations of the full open defect.
dc.description.abstract	Award-winning

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