Processors' design complexity increases with transistors' growing density. At the same time, market competence requires a decreasing time-to-market, and therefore, reduced validation time. Such time reduction imposes new challenges to post-Si validation strategies, processes, techniques, tools, and microprocessor hardware features. In this paper we develop a micro architectural technique to speed up the post-Si validation for one of the most complex and difficult to debug control logic pieces in the processor: the control flow recovery mechanisms used by control flow speculation, interrupts and exceptions. Our experiments show that with a small area overhead of 0.14% all post-Si bugs in this complex hardware can be detected in a timely manner, which avoids state pollution and reduces debug time.

Peer Reviewed