Fast time-to-market with via-configurable transistor array regular fabric: A delay-locked loop design case study

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To access the full text documents, please follow this link: http://hdl.handle.net/2117/15703

dc.contributor	Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.contributor	Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica
dc.contributor	Universitat Politècnica de Catalunya. MNT - Grup de Recerca en Micro i Nanotecnologies
dc.contributor	Universitat Politècnica de Catalunya. HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions
dc.contributor	Universitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors
dc.contributor	Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
dc.contributor.author	González Colás, Antonio María
dc.contributor.author	Pons Solé, Marc
dc.contributor.author	Barajas Ojeda, Enrique
dc.contributor.author	Mateo Peña, Diego
dc.contributor.author	López González, Juan Miguel
dc.contributor.author	Moll Echeto, Francisco de Borja
dc.contributor.author	Rubio Sola, Jose Antonio
dc.contributor.author	Abella Ferrer, Jaume
dc.contributor.author	Vera Rivera, Francisco Javier
dc.date	2011
dc.identifier.citation	Pons, M. [et al.]. Fast time-to-market with via-configurable transistor array regular fabric: A delay-locked loop design case study. A: Design and Technology of Integrated Systems. "Proc. of the Design and Technology of Integrated Systems". Atenes: IEEE Computer Society Publications, 2011, p. 1-6.
dc.identifier.citation	978-1-61284-899-0
dc.identifier.citation	10.1109/DTIS.2011.5941428
dc.identifier.uri	http://hdl.handle.net/2117/15703
dc.language.iso	eng
dc.publisher	IEEE Computer Society Publications
dc.relation	http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5941428
dc.rights	info:eu-repo/semantics/openAccess
dc.subject	Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
dc.subject	Microprocessors
dc.subject	Transistors
dc.subject	Transistors
dc.subject	Microprocessadors
dc.title	Fast time-to-market with via-configurable transistor array regular fabric: A delay-locked loop design case study
dc.type	info:eu-repo/semantics/publishedVersion
dc.type	info:eu-repo/semantics/conferenceObject
dc.description.abstract	Time-to-market is a critical issue for nowadays integrated circuits manufacturers. In this paper the Via-Configurable Transistor Array regular layout fabric (VCTA), which aims to minimize the time-to-market and its associated costs, is studied for a Delay-Locked Loop design (DLL). The comparison with a full custom design demonstrates that VCTA can be used without loss of functionality while accelerating the design time. Layout implementations, in 90 nm CMOS process, as well as the delay, energy and jitter electrical simulations are provided.
dc.description.abstract	Peer Reviewed

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