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| Title: | VHDL Implementation, Verification and Logic Synthesis of Memory Bus Arbiters for Multi-Processor System |
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| Author: | Sánchez López, Pedro Pascual |
| Other authors: | Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica; Septinus, Konstantin |
| Abstract: | |
| Subject(s): | -Àrees temàtiques de la UPC::Informàtica::Hardware -Multiprocessors -VHDL -Multi-core technology -Multiprocessadors |
| Rights: | Attribution-NonCommercial-NoDerivs 3.0 Spain
http://creativecommons.org/licenses/by-nc-nd/3.0/es/ |
| Document type: | Bachelor Thesis |
| Published by: | Universitat Politècnica de Catalunya |
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