2026-04-13T18:19:16Zhttps://recercat.cat/oai/request

oai:recercat.cat:2117/993982025-07-16T22:25:01Zcom_2072_1033col_2072_452949

Using LUT-specific delays to mitigate biases in delay-based PUFs and increase area efficiency on FPGAs Feiten, Linus Sauer, Matthias Becker, Bernd Àrees temàtiques de la UPC::Enginyeria electrònica Embedded computer systems--Congresses Integrated circuits Computer networks--Security measures Sistemes integrats -- Congressos Circuits integrats Seguretat informàtica -- Congressos 2016-11-14 Conference report Restricted access - confidentiality agreement east=2.11563799999999; north=41.38479239999999; name=Zona Universitària-Escola T S d'Enginyers, 08028 Barcelona, Espanya