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oai:recercat.cat:2117/4449472026-02-02T07:06:27Zcom_2072_1033col_2072_452950
RECERCAT author Andreu, Pablo author Alcaide Portet, Sergi author Lopez, Pedro author Abella Ferrer, Jaume author Hernandez, Carles 2025-01-02 The increased performance requirements of applications running on safety-critical systems have led to the use of complex platforms with several CPUs, GPUs, and AI accelerators. However, higher platform and system complexity challenge performance verification and validation since timing interference across tasks occurs in unobvious ways, hence defeating attempts to optimize application consolidation informedly during design phases and validating that mutual interference across tasks is within bounds during test phases. In that respect, the SafeSU has been proposed to extend inter-task interference monitoring capabilities in simple systems. However, modern mixed-criticality systems are complex, with multilayered interconnects, shared caches, and hardware accelerators. To that end, this paper proposes a non-intrusive add-on approach for monitoring interference across tasks in multilayer heterogeneous systems implemented by leveraging existing security frameworks and the SafeSU infrastructure. The feasibility of the proposed approach has been validated in an RTL RISC-V-based multicore SoC with support for AI hardware acceleration. Our results show that our approach can safely track contention and properly break down contention cycles across the different sources of interference, hence guiding optimization and validation processes.This work has received funding from the Chips Joint Undertaking project ISOLDE no. 101112274 and the Spanish Agencia Estatal de Investigación PCI2023-143358 grant. Pablo Andreu has received funding from Generalitat Valenciana, Spain via “Subvenciones para la contratación de personal investigador predoctoral” with reference CIACIF/2021/412. Carles Hernández is partially supported by Spanish Ministry of Science, Innovation and Universities under “Ramón Cajal”, fellowship No. RYC2020-030685-I. Funding for open access charge: CRUE-Universitat Politecnica de Valencia .Peer ReviewedPostprint (published version) http://creativecommons.org/licenses/by/4.0/ Open Access Attribution 4.0 International Àrees temàtiques de la UPC::Informàtica::Automàtica i control Safety QoS Network on chip Mixed-criticality Multicore Expanding SafeSU capabilities by leveraging security frameworks for contention monitoring in complex SoCs Article