2026-04-17T05:20:52Zhttps://recercat.cat/oai/requestoai:recercat.cat:2117/3941772025-07-22T22:57:30Zcom_2072_1033col_2072_452951
RECERCAT
author
Torregrosa Ortego, Àlex
2023-06-26
Memory Controllers play a crucial role in modern systems, being the last stop before accessing memory. DRAM memories require complex access patterns, which make the Controller responsible for orchestrating memory requests and optimizing their access sequences to maximize bandwidth. This project covers the design and implementation of a LPDDR4 Memory Controller. The overall design of the memory controller is described, as well as the rationale behind it. The different architectural and timing constraints, given by the LPDDR4 specification, are also studied, as well as the communication interfaces of the Controller with adjacent modules. Finally, the performance of the controller and various available address mappings is studied, showing how it is able to reach peak bandwidth. Its area and timing characteristics are also analyzed, confirming that it can reach the required operating conditions.
Restricted access - confidentiality agreement
Àrees temàtiques de la UPC::Informàtica::Programació
Device drivers (Computer programs)
LPDDR4
DFI
PHY
AXI
controlador de memòria
Memory Controller
Programes controladors
RTL implementation of a LPDDR4 Memory Controller
Master thesis