2026-04-13T03:59:16Zhttps://recercat.cat/oai/request

oai:recercat.cat:2117/3941762026-01-18T06:53:11Zcom_2072_1033col_2072_452950

Design and simulation of peripheral driving circuitry for computational ReRAM Diseño y simulación de circuito periférico de actuación para ReRAM computacional Fernández López, Cristina Vourkas, Ioannis Rubio Sola, Jose Antonio Àrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats Àrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Processadors digitals Integrated circuits Random access memory Memristor Resistive switching Resistive RAM ReRAM In-memory computing Ratioed logic gates LTSpice Circuits integrats Memòria d'accés aleatori © 2023 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. As an alternative approach to the von Neumann architecture, the notion of computational resistive random- access memory (ReRAM) has emerged, promising faster and more energy-efficient computing systems. In this context, we present a classification of ReRAM-compatible logic design strategies and highlight the potential of nonstateful ratioed logic for computational ReRAM modules. We provide insights towards the design of ad-hoc peripheral circuitry that allows the fusion of memory and ratioed logic operations in the ReRAM module in a reliable manner; i.e., the driving/sensing circuitry allows carrying out memory operations and in-memory multi- level ratioed logic operations. To this end, we present in detail a computational ReRAM driver and focus our description on the operational features that enable memory/logic operations in every row of the crossbar array. We validate circuit functionality through LTSpice simulations for read/write memory and logic operations using a threshold-type bipolar ReRAM device model. The presented practical solutions contribute to the viable development of computational ReRAM. Supported by Synopsys, Chile, by the Chilean grants FONDECYT Regular 1221747 and ANID-Basal FB0008, by the UTFSM Initiation in Scientific Investigation Program (PIIC) grant 016/2021, and by the Spanish MCIN/AEI/10.13039/501100011033 grant PID2019-103869RB-C33. Peer Reviewed Postprint (author's final draft) 2022 Conference report https://ieeexplore.ieee.org/document/9970082 info:eu-repo/grantAgreement/AEI/Plan Estatal de Investigación Científica y Técnica y de Innovación 2017-2020/PID2019-103869RB-C33 Open Access Institute of Electrical and Electronics Engineers (IEEE)