2026-04-18T05:56:27Zhttps://recercat.cat/oai/request

oai:recercat.cat:2117/3903962026-01-30T09:17:24Zcom_2072_1033col_2072_452950

00925njm 22002777a 4500 dc López Paradís, Guillem author Li, Brian author Armejach Sanosa, Adrià author Wallentowitz, Stefan author Moretó Planas, Miquel author Balkind, Jonathan author 2023 Chips with tens of billions of transistors have become today's norm. These designs are straining our electronic design automation tools throughout the design process, requiring ever more computational resources. In many tools, parallelisation has improved both latency and throughput for the designer's benefit. However, tools largely remain restricted to a single machine and in the case of RTL simulation, we believe that this leaves much potential performance on the table. We introduce Metro-MPI to improve RTL simulation for modern 10 billion transistor-scale chips. Metro-MPI exploits the natural boundaries present in chip designs to partition RTL simulations and leverage High Performance Computing (HPC) techniques to extract parallelism. For chip designs that scale in size by exploiting latency-insensitive interfaces like networks-on-chip and AXI, Metro-MPI offers a new paradigm for RTL simulation scalability. Our implementation of Metro-MPI in Open-Piton+Ariane delivers 2.7 MIPS of RTL simulation throughput for the first time on a design with more than 10 billion transistors and 1,024 Linux-capable cores, opening new avenues for distributed RTL simulation of emerging system-on-chip designs. Compared to sequential and multithreaded RTL simulations of smaller designs, Metro-MPI achieves up to 135.98× and 9.29× speedups. Similarly, for a representative regression run, Metro-Mpireduces energy consumption by up to 2.53× and 2.91× . This work has been partially supported by the Spanish Ministry of Economy and Competitiveness (contract PID2019-107255GB-C21), by the Generalitat de Catalunya (contract 2017-SGR-1328), by the European Union within the framework of the ERDF of Catalonia 2014-2020 under the DRAC project [001-P-001723], and by the Arm-BSC Center of Excellence. G. Lopez-Paradís has been supported by the Generalitat de Catalunya through a FI fellowship 2021FI-B00994 and GSoC 2021, and M. Moreto by a Ramon y Cajal fellowship no. RYC-2016-21104. A. Armejach is a Serra Hunter Fellow. Peer Reviewed Postprint (author's final draft) Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors High performance computing Networks on a chip Parallel processing (Electronic computers) RTL Simulation MPI Network-on-Chip Verilator Càlcul intensiu (Informàtica) Xarxes en xip Processament en paral·lel (Ordinadors) Fast behavioural RTL simulation of 10B transistor SoC designs with Metro-Mpi