<?xml version="1.0" encoding="UTF-8"?><?xml-stylesheet type="text/xsl" href="static/style.xsl"?><OAI-PMH xmlns="http://www.openarchives.org/OAI/2.0/" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.openarchives.org/OAI/2.0/ http://www.openarchives.org/OAI/2.0/OAI-PMH.xsd"><responseDate>2026-04-17T16:13:45Z</responseDate><request verb="GetRecord" identifier="oai:www.recercat.cat:2117/386166" metadataPrefix="qdc">https://recercat.cat/oai/request</request><GetRecord><record><header><identifier>oai:recercat.cat:2117/386166</identifier><datestamp>2025-07-17T03:56:35Z</datestamp><setSpec>com_2072_1033</setSpec><setSpec>col_2072_452950</setSpec></header><metadata><qdc:qualifieddc xmlns:qdc="http://dspace.org/qualifieddc/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:dcterms="http://purl.org/dc/terms/" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:doc="http://www.lyncode.com/xoai" xsi:schemaLocation="http://purl.org/dc/elements/1.1/ http://dublincore.org/schemas/xmls/qdc/2006/01/06/dc.xsd http://purl.org/dc/terms/ http://dublincore.org/schemas/xmls/qdc/2006/01/06/dcterms.xsd http://dspace.org/qualifieddc/ http://www.ukoln.ac.uk/metadata/dcmi/xmlschema/qualifieddc.xsd">
   <dc:title>Reusable Verification Environment for a RISC-V Vector Accelerator</dc:title>
   <dc:creator>Quiroga, Josue</dc:creator>
   <dc:creator>Genovese, Roberto Ignacio</dc:creator>
   <dc:creator>Díaz, Ivan</dc:creator>
   <dc:creator>Yano, Henrique</dc:creator>
   <dc:creator>Ali, Asif</dc:creator>
   <dc:creator>Sommez, Nehir</dc:creator>
   <dc:creator>Palomar Pérez, Óscar</dc:creator>
   <dc:creator>JImenez, Victor</dc:creator>
   <dc:creator>Rodriguez, Mario</dc:creator>
   <dc:creator>Dominguez, Marc</dc:creator>
   <dc:subject>Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors</dc:subject>
   <dc:subject>Open source software</dc:subject>
   <dc:subject>Verification</dc:subject>
   <dc:subject>Risc-V</dc:subject>
   <dc:subject>Vector Accelerator</dc:subject>
   <dc:subject>UVM</dc:subject>
   <dc:subject>Coverage</dc:subject>
   <dc:subject>Random Binary Generation</dc:subject>
   <dcterms:abstract>This paper presents a reusable verification environment developed for the verification of an academic&#xd;
RISC-V based vector accelerator that operates with long vectors. In order to be used across diverse projects, this&#xd;
infrastructure intends to be independent of the interface used for connecting the accelerator to the scalar processor&#xd;
core. We built a verification infrastructure consisting of a Universal Verification Environment (UVM) which is&#xd;
capable of validating the design performing co-simulation of the vector instructions. Moreover, we provided a set of&#xd;
tests and an automated test generation, simulation and error reporting infrastructure. This paper shares our&#xd;
experience on verifying a complex accelerator used in two distinct projects, with different interfaces.</dcterms:abstract>
   <dcterms:abstract>This research has received funding from the European High Performance Computing Joint Undertaking (JU)&#xd;
under Framework Partnership Agreement No 800928 (European Processor Initiative) and Specific Grant&#xd;
Agreement No 101036168 (EPI SGA2) and No 956702 (eProcessor) . The JU receives support from the&#xd;
European Union’s Horizon 2020 research and innovation programme and from Croatia, France, Germany,&#xd;
Greece, Italy, Netherlands, Portugal, Spain, Sweden, and Switzerland. The EPI-SGA2 project,&#xd;
PCI2022-132935_N1618737 is also co-funded by MCIN/AEI /10.13039/501100011033 and by the UE&#xd;
NextGenerationEU/PRTR</dcterms:abstract>
   <dcterms:abstract>Peer Reviewed</dcterms:abstract>
   <dcterms:abstract>Postprint (author's final draft)</dcterms:abstract>
   <dcterms:issued>2023</dcterms:issued>
   <dc:type>Conference lecture</dc:type>
   <dc:relation>https://dvcon-proceedings.org/document/reusable-verification-environment-for-a-risc-v-vector-accelerator/</dc:relation>
   <dc:relation>info:eu-repo/grantAgreement/EC/H2020/101036168/EU/European Processor Initiative/EPI SGA2</dc:relation>
   <dc:relation>info:eu-repo/grantAgreement/EC/H2020/956702/EU/European, extendable, energy-efficient, energetic, embedded, extensible, Processor Ecosystem/eProcessor</dc:relation>
   <dc:rights>Open Access</dc:rights>
   <dc:publisher>Accellera Systems Initiative (Accellera)</dc:publisher>
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