2026-04-17T11:36:51Zhttps://recercat.cat/oai/request

oai:recercat.cat:2117/3814742026-01-27T04:13:22Zcom_2072_1033col_2072_452950

00925njm 22002777a 4500 dc Fernandez Hernandez, Carlos author Vourkas, Ioannis author Rubio Sola, Jose Antonio author 2022 © 2022 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. Emerging memory technologies will play a decisive role in the quest for more energy-efficient computing systems. Computational ReRAM structures based on resistive switching devices (memristors) have been explored for in-memory computations using the resistance of ReRAM cells for storage and for logic I/O representation. Such approach presents three major challenges: the support for a memristor-oriented logic style, the ad-hoc design of memory array driving circuitry for memory and logic operations, and the development of dedicated synthesis tools to instruct the multi-level operations required for the execution of an arbitrary logic function in memory. This work contributes towards the development of an automated design flow for ReRAM-based computational memories, highlighting some important HW-SW co-design considerations. We briefly present a case study concerning a synthesis flow for a nonstateful logic style and the co-design of the underlying 1T1R crossbar array driving circuit. The prototype of the synthesis flow is based on the ABC tool and the Z3 solver. It executes fast owing to the level-by-level mapping of logic gates. Moreover, it delivers a mapping that minimizes the logic function latency through parallel logic operations, while also using the less possible ReRAM cells. Supported by Synopsys, Chile, by the Chilean grants FONDECYT Regular 1221747 and ANID-Basal FB0008, and by the Spanish MCIN/AEI/10.13039/501100011033 grant PID2019-103869RB-C33 Peer Reviewed Postprint (author's final draft) Àrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats Integrated circuits Electronic design automation In-memory computing Logic synthesis Memristor Ratioed logic Resistive RAM Computation theory Computer circuits Energy efficiency Logic circuits Logic Synthesis Mapping Memory architecture Memristors Timing circuits Co-designs Electronics design automation Emerging memory technologies Energy-efficient computing In-memory computing Logic functions Logic operations Logic style Memristor Ratioed logic RRAM Circuits integrats Circuit topology and synthesis flow co-design for the development of computational ReRAM