2026-04-14T02:49:57Zhttps://recercat.cat/oai/request

oai:recercat.cat:2117/3761302025-07-23T03:18:46Zcom_2072_1033col_2072_452951

Verification of a microprocessor's memory pipeline with UVM Sans Prats, Josep Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors Espasa Sans, Roger Marcuello, Pedro Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors Verilog (Computer hardware description language) Verificació UVM SystemVerilog Hardware Generació de tests Verification Test Generation Verilog (Llenguatge de descripció del maquinari) This thesis presents the contributions made in the environment developed for the verification of the memory pipeline of a RISC-V core. A UVM testbench, along with a golden model, has been developed which is able to functionally verify the behaviour of the memory pipeline. To generate tests to stress the different functionalities of the memory pipeline, a test generation flow based on a genetic algorithm has been set up. With it, several issues on the memory pipeline logic have been found, and helped improving the RTL logic of the design. 2022-07-01 Master thesis https://hdl.handle.net/2117/376130 171946 eng Restricted access - author's decision application/pdf Universitat Politècnica de Catalunya