2026-04-17T06:42:44Zhttps://recercat.cat/oai/request

oai:recercat.cat:2117/3740592026-01-30T07:16:25Zcom_2072_1033col_2072_452950

OmpSs@cloudFPGA: An FPGA task-based programming model with message passing De Haro Ruiz, Juan Miguel Cano, Rubén Álvarez Martínez, Carlos Jiménez González, Daniel Martorell Bofill, Xavier Ayguadé Parra, Eduard Labarta Mancho, Jesús José Abel, François Ringlein, Burkhard Weiss, Beat Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors::Arquitectures paral·leles Supercomputers -- Energy consumption Application program interfaces (Computer software) Parallel processing (Electronic computers) FPGA MPI OpenMP Programming models Network-attached FPGA Stand-alone FPGA High-level synthesis Heterogeneous programming High-performance computing Supercomputadors -- Consum d'energia Interfícies de programació d'aplicacions (Programari) Processament en paral·lel (Ordinadors) Nowadays, a new parallel paradigm for energy-efficient heterogeneous hardware infrastructures is required to achieve better performance at a reasonable cost on high-performance computing applications. Under this new paradigm, some application parts are offloaded to specialized accelerators that run faster or are more energy-efficient than CPUs. Field-Programmable Gate Arrays (FPGA) are one of those types of accelerators that are becoming widely available in data centers. This paper proposes OmpSs@cloudFPGA, which includes novel extensions to parallel task-based programming models that enable easy and efficient programming of heterogeneous clusters with FPGAs. The programmer only needs to annotate, with OpenMP-like pragmas, the tasks of the application that should be accelerated in the cluster of FPGAs. Next, the proposed programming model framework automatically extracts parts annotated with High-Level Synthesis (HLS) pragmas and synthesizes them into hardware accelerator cores for FPGAs. Additionally, our extensions include and support two novel features: 1) FPGA-to-FPGA direct communication using a Message Passing Interface (MPI) similar Application Programming Interface (API) with one-to-one and collective communications to alleviate host communication channel bottleneck, and 2) creating and spawning work from inside the FPGAs to their own accelerator cores based on an MPI rank-like identification. These features break the classical host-accelerator model, where the host (typically the CPU) generates all the work and distributes it to each accelerator. We also present an evaluation of OmpSs@cloudFPGA for different parallel strategies of the N-Body application on the IBM cloudFPGA research platform. Results show that for cluster sizes up to 56 FPGAs, the performance scales linearly. To the best of our knowledge, this is the best performance obtained for N-body over FPGA platforms, reaching 344 Gpairs/s with 56 FPGAs. Finally, we compare the performance and power consumption of the proposed approach with the ones obtained by a classical execution on the MareNostrum 4 supercomputer, demonstrating that our FPGA approach reduces power consumption by an order of magnitude. This work has been done in the context of the IBM/BSC Deep Learning Center initiative. This work has received funding from the European Union’s Horizon 2020 research and innovation programme under grant agreement No 754337 (EuroEXA), from Spanish Government (PID2019-107255GBC21/AEI/10.13039/501100011033), and from Generalitat de Catalunya (2017-SGR-1414 and 2017-SGR-1328). Peer Reviewed Postprint (author's final draft) 2022 Conference report https://ieeexplore.ieee.org/document/9820636 info:eu-repo/grantAgreement/EC/H2020/754337/EU/Co-designed Innovation and System for Resilient Exascale Computing in Europe: From Applications to Silicon/EuroEXA info:eu-repo/grantAgreement/AEI/Plan Estatal de Investigación Científica y Técnica y de Innovación 2017-2020/PID2019-107255GB-C21/ES/BSC - COMPUTACION DE ALTAS PRESTACIONES VIII/ Open Access Institute of Electrical and Electronics Engineers (IEEE)