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oai:recercat.cat:2117/3699672025-07-16T22:40:02Zcom_2072_1033col_2072_452949

VES2 - DFT and Functional Safety Eggersgluess, Stephan Harrison, Lee Àrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica Microelectronics Integrated circuits Spinitronics Microelectrònica Circuits integrats Espintrònica Machine Learning for DFT and ATPG Yu HUANG (HiSILICON Inc. – China) Functional Safety Challenges and Solutions for the ARM® MaliTM-G78AE GPU Prashant KULKARNI, Kartik KATHURIA (ARM – United Kingdom), Jussi PENNALA (ARM – Sweden) 3D IC DFT Implementation and Interconnect Test Based on IEEE 1838 Lukasz KOTYNIA, Frederic AZOULAY, Vivek CHICKERMANE, Sagar KUMAR, Rajesh KHURANA (CADENCE Design Systems – POLAND, US) 2022-05 Conference report Eggersgluess, S.; Harrison, L. Vendor Session 2: DFT and Functional Safety. A: 27th IEEE European Test Symposium (ETS). 2022, https://hdl.handle.net/2117/369967 eng http://creativecommons.org/licenses/by-nc-nd/4.0/ Open Access Attribution-NonCommercial-NoDerivatives 4.0 International 1 p. application/pdf