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Towards reconfigurable accelerators in HPC: Designing a multipurpose eFPGA tile for heterogeneous SoCs Hotfilter, Tim Kreß, Fabian Kempf, Fabian Becker, Jürgen De Haro Ruiz, Juan Miguel Jiménez González, Daniel Moretó Planas, Miquel Álvarez Martínez, Carlos Labarta Mancho, Jesús José Baili, Imen Universitat Politècnica de Catalunya. Doctorat en Arquitectura de Computadors Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors Barcelona Supercomputing Center Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors Field programmable gate arrays High performance computing -- Energy consumption Logic design FPGA HPC Design space exploration SoC Matrius de portes programables per l'usuari Càlcul intensiu (Informàtica) -- Consum d'energia Estructura lògica The goal of modern high performance computing platforms is to combine low power consumption and high throughput. Within the European Processor Initiative (EPI), such an SoC platform to meet the novel exascale requirements is built and investigated. As part of this project, we introduce an embedded Field Programmable Gate Array (eFPGA), adding flexibility to accelerate various workloads. In this article, we show our approach to design the eFPGA tile that supports the EPI SoC. While eFPGAs are inherently reconfigurable, their initial design has to be determined for tape-out. The design space of the eFPGA is explored and evaluated with different configurations of two HPC workloads, covering control and dataflow heavy applications. As a result, we present a well-balanced eFPGA design that can host several use cases and potential future ones by allocating 1% of the total EPI SoC area. Finally, our simulation results of the architectures on the eFPGA show great performance improvements over their software counterparts. European Processor Initiative (EPI) project has received funding from the European Union’s Horizon 2020 research and innovation programme under grant agreement No. 826647, from Spanish Government (PID2019- 107255GB-C21/AEI /10.13039/501100011033), and from Generalitat de Catalunya (contracts 2017-SGR-1414 and 2017-SGR-1328). M. Moreto is partially supported by the Spanish Ministry of Economy, Industry and Competitiveness under Ramon y Cajal fellowship No. RYC-2016-21104. Peer Reviewed Postprint (author's final draft) 2022 Conference report Hotfilter, T. [et al.]. Towards reconfigurable accelerators in HPC: Designing a multipurpose eFPGA tile for heterogeneous SoCs. A: Design, Automation and Test in Europe Conference and Exhibition. "Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE 2022): 14-23 March 2022, online virtual platform". Institute of Electrical and Electronics Engineers (IEEE), 2022, p. 628-631. ISBN 978-3-9819263-6-1. DOI 10.23919/DATE54114.2022.9774716. 978-3-9819263-6-1 https://hdl.handle.net/2117/367987 10.23919/DATE54114.2022.9774716 eng https://ieeexplore.ieee.org/document/9774716 info:eu-repo/grantAgreement/EC/H2020/826647/EU/SGA1 (Specific Grant Agreement 1) OF THE EUROPEAN PROCESSOR INITIATIVE (EPI)/EPI SGA1 Open Access 4 p. application/pdf Institute of Electrical and Electronics Engineers (IEEE)