2026-04-05T10:50:58Zhttps://recercat.cat/oai/request

oai:recercat.cat:2117/3527032026-02-11T06:10:58Zcom_2072_1033col_2072_452950

Mont-Blanc 2020: Towards scalable and power efficient European HPC processors Armejach Sanosa, Adrià Brank, Bine Cortina Guardia, Jordi Dolique, François Hayes, Timothy Ho, Nam Lagadec, Pierre-Axel Lemaire, Romain López Paradís, Guillem Marliac, Laurent Moretó Planas, Miquel Marcuello Pascual, Pedro Pleiter, Dirk Tan, Xubin Derradji, Said Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors Big data High performance computing Systems on a chip Economics Context Europe Computer architecture Dades massives Càlcul intensiu (Informàtica) Sistemes monoxip The Mont-Blanc 2020 (MB2020) project has triggered the development of the next generation industrial processor for Big Data and High Performance Computing (HPC). MB2020 is paving the way to the future low-power European processor for exascale, defining the System-on-Chip (SoC) architecture and implementing new critical building blocks to be integrated in such an SoC. In this paper, we first present an overview of the MB2020 project, then we describe our experimental infrastructure, the requirements of relevant applications, and the IP blocks developed in the project. Finally, we present our emulation-based final demonstrator and explain how it integrates within our first generation of HPC processors. This work is supported by the European Community’s Horizon 2020 Framework Programme under the Mont-Blanc 2020 project, grant agreement n. 779877. Peer Reviewed Postprint (author's final draft) 2021 Conference report https://ieeexplore.ieee.org/document/9474093 info:eu-repo/grantAgreement/EC/H2020/779877/EU/Mont-Blanc 2020, European scalable, modular and power efficient HPC processor/Mont-Blanc 2020 Open Access Institute of Electrical and Electronics Engineers (IEEE)