2026-04-17T23:01:39Zhttps://recercat.cat/oai/request

oai:recercat.cat:2117/3457932025-07-22T18:04:51Zcom_2072_1033col_2072_452951

Design of a clock and data recovery circuit in FDSOI technology for high speed serial links Safadi Figueroa, Hugo Ernesto Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica Moll Echeto, Francisco de Borja Mateo Peña, Diego Àrees temàtiques de la UPC::Enginyeria electrònica Low voltage systems Electronic circuits CDR PLL FDSOI VCO jitter phase noise. Baixa tensió Circuits electrònics The purpose of this thesis is to design an 8 Gbps clock and data recovery circuit intended to work in the receiver of a high-speed Serializer-Deserializer interface (SerDes). The proposed architecture is based on a phase-locked loop operation (PLL) that integrates a linear phase detector, a charge pump, a wide-tuning range voltage-controlled ring oscillator (2.5- 12 GHz), and a third order low pass filter that achieves a bandwidth of 150 MHz. A wide loop bandwidth is considered in the design to achieve a high input jitter tolerance and a fast locking time. Implemented in 22 nm FDSOI, the overall circuit draws 1.38mW from a 0.8V power supply, exhibits a recovery clock RMS jitter of 0.970 fs and and requires a locking time of 22 ns. A Monte Carlo analysis has been performed applying temperature and voltage corners of -40 C to 125 C and 0.72 V to 0.88 V respectively. The results indicated a 95.6% success rate. By using an external voltage that has been implemented to adjust the phase detector's bias current, 100% success rate is achieved. 2021-03 Master thesis https://hdl.handle.net/2117/345793 ETSETB-230.156970 eng S'autoritza la difusió de l'obra mitjançant la llicència Creative Commons o similar 'Reconeixement-NoComercial- SenseObraDerivada' Open Access application/pdf Universitat Politècnica de Catalunya