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oai:recercat.cat:2117/275202026-02-09T08:48:49Zcom_2072_1033col_2072_452950

00925njm 22002777a 4500 dc Slijepcevic, Mladen author Kosmidis, Leonidas author Abella Ferrer, Jaume author Quiñones, Eduardo author Cazorla, Francisco J. author 2014-11-01 Critical real-time embedded systems feature complex safety-related, performance-demanding functionality. High-performance hardware and software can provide such functionality, but the use of aggressive technologies and architectures challenges time predictability and reliability. The authors propose a new approach to obtain trustworthy worst-case execution time estimates for safety-critical applications running on high-performance faulty hardware by using both timing-analysis techniques and minor hardware modifications. Peer Reviewed Postprint (published version) Àrees temàtiques de la UPC::Informàtica Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors::Arquitectures paral·leles Fault-tolerant computing Embedded computer systems Systems Caches Embedded systems Fault tolerant computing Formal verification Parallel processing Program diagnostics Safety-critical software Tolerància als errors (Informàtica) Sistemes incrustats (Informàtica) Timing verification of fault-tolerant chips for safety-critical applications in harsh environments