<?xml version="1.0" encoding="UTF-8"?><?xml-stylesheet type="text/xsl" href="static/style.xsl"?><OAI-PMH xmlns="http://www.openarchives.org/OAI/2.0/" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.openarchives.org/OAI/2.0/ http://www.openarchives.org/OAI/2.0/OAI-PMH.xsd"><responseDate>2026-04-17T05:31:30Z</responseDate><request verb="GetRecord" identifier="oai:www.recercat.cat:2117/22448" metadataPrefix="oai_dc">https://recercat.cat/oai/request</request><GetRecord><record><header><identifier>oai:recercat.cat:2117/22448</identifier><datestamp>2026-01-21T06:29:15Z</datestamp><setSpec>com_2072_1033</setSpec><setSpec>col_2072_452950</setSpec></header><metadata><oai_dc:dc xmlns:oai_dc="http://www.openarchives.org/OAI/2.0/oai_dc/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:doc="http://www.lyncode.com/xoai" xsi:schemaLocation="http://www.openarchives.org/OAI/2.0/oai_dc/ http://www.openarchives.org/OAI/2.0/oai_dc.xsd">
   <dc:title>A cache design for probabilistically analysable real-time systems</dc:title>
   <dc:creator>Kosmidis, Leonidas</dc:creator>
   <dc:creator>Abella Ferrer, Jaume</dc:creator>
   <dc:creator>Quiñones, Eduardo</dc:creator>
   <dc:creator>Cazorla Almeida, Francisco Javier</dc:creator>
   <dc:contributor>Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors</dc:contributor>
   <dc:subject>Àrees temàtiques de la UPC::Informàtica::Hardware</dc:subject>
   <dc:subject>Embedded computer systems</dc:subject>
   <dc:subject>Fault-tolerant computing</dc:subject>
   <dc:subject>Amount of information</dc:subject>
   <dc:subject>Cache access</dc:subject>
   <dc:subject>Hardware complexity</dc:subject>
   <dc:subject>Hardware design</dc:subject>
   <dc:subject>Random placement</dc:subject>
   <dc:subject>Set-associative</dc:subject>
   <dc:subject>Timing Analysis</dc:subject>
   <dc:subject>Wcet analysis</dc:subject>
   <dc:subject>Tolerància als errors (Informàtica)</dc:subject>
   <dc:subject>Sistemes incrustats (Informàtica)</dc:subject>
   <dc:description>Caches provide significant performance improvements, though their use in real-time industry is low because current WCET analysis tools require detailed knowledge of program's cache accesses to provide tight WCET estimates. Probabilistic Timing Analysis (PTA) has emerged as a solution to reduce the amount of information needed to provide tight WCET estimates, although it imposes new requirements on hardware design. At cache level, so far only fully-associative random-replacement caches have been proven to fulfill the needs of PTA, but they are expensive in size and energy. In this paper we propose a cache design that allows setassociative and direct-mapped caches to be analysed with PTA techniques. In particular we propose a novel parametric random placement suitable for PTA that is proven to have low hardware complexity and energy consumption while providing comparable performance to that of conventional modulo placement.</dc:description>
   <dc:description>Peer Reviewed</dc:description>
   <dc:description>Postprint (published version)</dc:description>
   <dc:date>2013</dc:date>
   <dc:type>Conference report</dc:type>
   <dc:identifier>Kosmidis, L. [et al.]. A cache design for probabilistically analysable real-time systems. A: Design, Automation and Test in Europe. "Design, Automation and Test in Europe: Grenoble, France, March 18 - 22, 2013". Grenoble: 2013, p. 513-518.</dc:identifier>
   <dc:identifier>978-398153700-0</dc:identifier>
   <dc:identifier>https://hdl.handle.net/2117/22448</dc:identifier>
   <dc:language>eng</dc:language>
   <dc:relation>http://dl.acm.org/citation.cfm?id=2485288.2485416</dc:relation>
   <dc:rights>http://creativecommons.org/licenses/by-nc-nd/3.0/es/</dc:rights>
   <dc:rights>Restricted access - publisher's policy</dc:rights>
   <dc:rights>Attribution-NonCommercial-NoDerivs 3.0 Spain</dc:rights>
   <dc:format>6 p.</dc:format>
   <dc:format>application/pdf</dc:format>
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