2026-04-17T14:10:54Zhttps://recercat.cat/oai/request

oai:recercat.cat:2117/200342026-02-07T08:30:58Zcom_2072_1033col_2072_452950

Producer-consumer: the programming model for future many-core processors Prat Pérez, Arnau Domínguez Sal, David Larriba Pey, Josep Troncoso, Pedro Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors Universitat Politècnica de Catalunya. DAMA-UPC - Data Management Group Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors Computer architecture Data parallelism Execution time Graph-based Main memory Many-core processors Model scale Off-chip memories On chip memory Programming models Single-chip cloud computers Arquitectura d'ordinadors The massive addition of cores on a chip is adding more pressure to the accesses to main memory. In order to avoid this bottleneck, we propose the use of a simple producer-consumer model, which allows for the temporary results to be transferred directly from one task to another. These data transfer operations are performed within the chip, using on-chip memory, thus avoiding costly off-chip memory accesses. We implement this model on a real many-core processor, the 48-core Intel Single-chip Cloud Computer processor using its on-chip memory facilities. We find that the Producer-Consumer model adapts to such architectures and allow to achieve good task and data parallelism. For the evaluation of the proposed platform we implement a graph-based application using the Producer- Consumer model. Our tests show that the model scales very well as it takes advantage of the on-chip memory. The execution times of our implementation are up to 9 times faster than the baseline implementation, which relies on storing the temporary results to main memory. Peer Reviewed Postprint (published version) 2013 Conference report Prat, A. [et al.]. Producer-consumer: the programming model for future many-core processors. A: International Conference on Architecture of Computing Systems. "ARCS 2013: 26th International Conference on Architecture of Computing Systems: Prague, Czech Republic: February 19-22, 2013: proceedings". Praga: Springer, 2013, p. 110-121. 978-364236423-5 https://hdl.handle.net/2117/20034 10.1007/978-3-642-36424-2_10 eng http://dl.acm.org/citation.cfm?id=2450037 info:eu-repo/grantAgreement/EC/FP7/287759/EU/High Performance and Embedded Architecture and Compilation/HIPEAC http://creativecommons.org/licenses/by-nc-nd/3.0/es/ Restricted access - publisher's policy Attribution-NonCommercial-NoDerivs 3.0 Spain 12 p. application/pdf Springer