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               <mods:name>
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                     <mods:roleTerm type="text">author</mods:roleTerm>
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                  <mods:namePart>Bergas Jané, Joan Gabriel</mods:namePart>
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               <mods:name>
                  <mods:role>
                     <mods:roleTerm type="text">author</mods:roleTerm>
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                  <mods:namePart>Ferrater Simón, María Misericordia</mods:namePart>
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               <mods:name>
                  <mods:role>
                     <mods:roleTerm type="text">author</mods:roleTerm>
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                  <mods:namePart>Gross, Gabriel Igor</mods:namePart>
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               <mods:name>
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                     <mods:roleTerm type="text">author</mods:roleTerm>
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                  <mods:namePart>Ramírez Pisco, Rodrigo</mods:namePart>
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               <mods:name>
                  <mods:role>
                     <mods:roleTerm type="text">author</mods:roleTerm>
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                  <mods:namePart>Galceran Arellano, Samuel</mods:namePart>
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               <mods:name>
                  <mods:role>
                     <mods:roleTerm type="text">author</mods:roleTerm>
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                  <mods:namePart>Rull Duran, Joan</mods:namePart>
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               <mods:originInfo>
                  <mods:dateIssued encoding="iso8601">2011-04-19</mods:dateIssued>
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               <mods:abstract>In this article, a high-accuracy all-digital resolverto-&#xd;
digital converter is presented. The two basic components of&#xd;
a conventional tracking R/D converter, the phase detector and&#xd;
the loop filter, are software implemented by frequency shifting&#xd;
techniques and a decoupled Double Synchronous Rotating&#xd;
reference Frame-based PLL (DSRF-PLL). This PLL allows the&#xd;
simultaneous extraction of the angular position and speed of the&#xd;
rotatory resolver, even in the presence of gain and phase errors&#xd;
in the resolver. In order to increase accuracy and to minimize&#xd;
the time lag of the whole system, oversampling methods and&#xd;
downsampling FIR digital filters are introduced. Finally, DSP&#xd;
implementation issues, like the use of techniques to synchronize&#xd;
the resolver output signals with the excitation one, are discussed.&#xd;
Using these combined techniques and a standard DSP with a&#xd;
12-bit ADC, resolutions of up to 14 bits can be achieved with&#xd;
a computation cost of about 13% of the total (100 MIPs). The&#xd;
paper presents the main techniques, simulation and experimental&#xd;
results.Postprint (published version)</mods:abstract>
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               <mods:accessCondition type="useAndReproduction">http://creativecommons.org/licenses/by-nc-nd/3.0/es/ Restricted access - publisher's policy Attribution-NonCommercial-NoDerivs 3.0 Spain</mods:accessCondition>
               <mods:subject>
                  <mods:topic>Àrees temàtiques de la UPC::Enginyeria de la telecomunicació::Processament del senyal::Filtres analògics i digitals</mods:topic>
               </mods:subject>
               <mods:subject>
                  <mods:topic>Variable speed drives</mods:topic>
               </mods:subject>
               <mods:subject>
                  <mods:topic>Electric filters, Digital</mods:topic>
               </mods:subject>
               <mods:subject>
                  <mods:topic>Filtres digitals</mods:topic>
               </mods:subject>
               <mods:titleInfo>
                  <mods:title>High-accuracy all-digital resolver-to-digital conversion</mods:title>
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               <mods:genre>Article</mods:genre>
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