2026-04-17T02:13:43Zhttps://recercat.cat/oai/request

oai:recercat.cat:2117/1309772026-01-21T08:49:04Zcom_2072_1033col_2072_452950

urn:hdl:2117/130977 Synchronous elastic networks Krstic, Sava Cortadella, Jordi Kishinevsky, Michael O'Leary, John Àrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats Logic circuits Circuits Adders Delay Timing Wires Process design Design methodology Control systems Communications technology Microarchitecture Circuits lògics We formally define - at the stream transformer level - a class of synchronous circuits that tolerate any variability in the latency of their environment. We study behavioral properties of networks of such circuits and prove fundamental compositionality results. The paper contributes to bridging the gap between the theory of latency-insensitive systems and the correct implementation of efficient control structures for them. Peer Reviewed Postprint (published version) 2006 Conference report https://ieeexplore.ieee.org/document/4021004 Open Access Institute of Electrical and Electronics Engineers (IEEE)