2026-04-17T02:53:45Zhttps://recercat.cat/oai/request

oai:recercat.cat:2117/1213862026-01-27T02:12:16Zcom_2072_1033col_2072_452950

00925njm 22002777a 4500 dc Rivas-Gomez, Sergio author Peña, Antonio J. author Moloney, David author Laure, Erwin author Markidis, Stefano author 2018-08-06 The success of the exascale supercomputer is largely debated to remain dependent on novel breakthroughs in technology that effectively reduce the power consumption and thermal dissipation requirements. In this work, we consider the integration of co-processors in high-performance computing (HPC) to enable low-power, seamless computation offloading of certain operations. In particular, we explore the so-called Vision Processing Unit (VPU), a highly-parallel vector processor with a power envelope of less than 1W. We evaluate this chip during inference using a pre-trained GoogLeNet convolutional network model and a large image dataset from the ImageNet ILSVRC challenge. Preliminary results indicate that a multi-VPU configuration provides similar performance compared to reference CPU and GPU implementations, while reducing the thermal-design power (TDP) up to 8x in comparison. The experimental results were performed on resources provided by the Swedish National Infrastructure for Computing (SNIC) at PDC Centre for High-Performance Com- puting (PDC-HPC). The work was funded by the European Commission through the SAGE project (Grant agreement no. 671500 / http://www.sagestorage.eu). Postprint (author's final draft) Àrees temàtiques de la UPC::Informàtica High performance computing Machine learning Vision Processing Unit High-Performance Computing Machine Learning Supercomputadors Exploring the Vision Processing Unit as Co-Processor for Inference