2026-04-17T11:45:28Zhttps://recercat.cat/oai/request

oai:recercat.cat:2117/113792026-02-07T06:55:07Zcom_2072_1033col_2072_452950

Interleaving granularity on high bandwidth memory architecture for CMPs Cabarcas, Felipe Rico Carro, Alejandro Etsion, Yoav Ramírez Bellido, Alejandro Computer storage devices -- Design and construction DRAM chips Interleaved storage Memory architecture Multiprocessing systems Memòria (informàtica) Memory bandwidth has always been a critical factor for the performance of many data intensive applications. The increasing processor performance, and the advert of single chip multiprocessors have increased the memory bandwidth demands beyond what a single commodity memory device can provide. The immediate solution is to use more than one memory device, and interleave data across them so they can be used in parallel as if they were a single device of higher bandwidth. In this paper we showed that fine-grain memory interleaving on the evaluated many-core architectures with many DRAM channels was critical to achieve high memory bandwidth efficiency. Our results showed that performance can degrade up to 50% due to achievable bandwidths being far from the maximum installed. Postprint (published version) 2010 Conference report http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5642060 Open Access IEEE Computer Society Publications